View CS5345-CQZ_1308616.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 104 db, 24-bit, 192 khz stereo audio adc a/d features ? multi-bit delta sigma modulator ? 104 db dynamic range ? -95 db thd+n ? stereo 6:1 input multiplexer ? programmable gain amplifier (pga) ? 12 db gain, 0.5 db step size ? zero crossing, click-free transitions ? stereo microphone inputs ? +32 db gain stage ? low-noise bias supply ? up to 192 khz sampling rates ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit ? high-pass filter or dc offset calibration system features ? power-down mode ? +3.3 v to +5 v analog power supply, nominal ? +3.3 v to +5 v digital power supply, nominal ? direct interface with 1.8 v to 5 v logic levels ? pin-compatible with cs4245 general description the cs5345 integrates an analog multiplexer, program- mable gain amplifier, and stereo audio analog-to-digital converter. the cs5345 perfor ms stereo analog-to-digi- tal (a/d) conversion of up to 24-bit serial values at sample rates up to 192 khz. a 6:1 stereo input multiplexe r is included for selecting between line-level and microphone-level inputs. the microphone input path includes a +32 db gain stage and a low-noise bias voltage supply. the pga is avail- able for line or microphone inputs and provides gain/attenuation of 12 db in 0.5 db steps. the output of the pga is followed by an advanced 5th- order, multi-bit delta sigma modulator and digital filter- ing/decimation. sampled data is transmitted by the serial audio interface at rates from 4 khz to 192 khz in either slave or master mode. integrated level translators allow easy interfacing be- tween the cs5345 and other devices operating over a wide range of logic levels. the cs5345 is available in a 48-pin lqfp package in commercial (-10 to +70 c) and automotive (-40 to +105 c) grade. the cdb5345 customer demonstra- tion board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 41 for complete details. 1.8 v to 5 v low-latency anti-alias filter internal voltage reference multibit oversampling adc multibit oversampling adc low-latency anti-alias filter high pass filter high pass filter stereo input 1 serial audio output 3.3 v to 5 v 3.3 v to 5 v mux pga pcm serial interface register configuration level translator left pga output right pga output stereo input 2 stereo input 3 stereo input 4 / mic input 1 & 2 stereo input 5 stereo input 6 pga +32 db +32 db level translator reset i2c/spi control data interrupt overflow august '07 ds658f2 cs5345
2 ds658f2 cs5345 table of contents 1. pin descriptions ...................................................................................................... ................... 5 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 7 specified operating conditions ............................................................................................. 7 absolute maximum ratings ...................................................................................................... .7 adc analog characteristics ................................................................................................... 8 adc analog characteristics ................................................................................................. 10 adc digital filter characteristics ..................................................................................... 11 pgaout analog characteristics .......................................................................................... 12 pgaout analog characteristics .......................................................................................... 13 pgaout analog characteristics .......................................................................................... 14 dc electrical characteristics ............................................................................................. 15 digital interface characteristics ...................................................................................... 16 switching characteristics - serial audio port ............................................................. 17 switching characteristics - control port - i2c format ............................................ 20 switching characteristics - control port - spi format ........................................... 21 3. typical connection diagram ................................................................................................. .. 22 4. applications ............................................................................................................... .................... 23 4.1 recommended power-up sequence ............................................................................................. 23 4.2 system clocking ........................................................................................................... .................. 23 4.2.1 master clock ............................................................................................................ ............. 23 4.2.2 master mode ............................................................................................................. ............ 24 4.2.3 slave mode .............................................................................................................. ............. 24 4.3 high-pass filter and dc offset calibration ................................................................................ .... 24 4.4 analog input multiplexer, pga, and mic gain ............................................................................... .25 4.5 input connections ......................................................................................................... .................. 25 4.6 pga auxiliary analog output ............................................................................................... .......... 25 4.7 control port description and timing ....................................................................................... ........ 26 4.7.1 spi mode ................................................................................................................ ............... 26 4.7.2 i2c mode ................................................................................................................ ................ 26 4.8 interrupts and overflow ................................................................................................... ............... 28 4.9 reset ..................................................................................................................... ......................... 28 4.10 synchronization of multiple devices ...................................................................................... ....... 28 4.11 grounding and power supply decoupling .................................................................................... 28 5. register quick reference ................................................................................................... ..... 30 6. register description ....................................................................................................... ........... 31 6.1 chip id - register 01h .................................................................................................... ................ 31 6.2 power control - address 02h ...................... ......................................................................... .......... 31 6.2.1 freeze (bit 7) .......................................................................................................... ............... 31 6.2.2 power-down mic (bit 3) .................................................................................................. ...... 31 6.2.3 power-down adc (bit 2) .................................................................................................. ..... 31 6.2.4 power-down device (bit 0) ............................................................................................... .... 31 6.3 adc control - address 04h ................................................................................................. ........... 32 6.3.1 functional mode (bits 7:6) .............................................................................................. ...... 32 6.3.2 digital interface format (b it 4) ........................................................................................ ...... 32 6.3.3 mute (bit 2) ............................................................................................................ ................ 32 6.3.4 high-pass filter freeze (b it 1) ......................................................................................... ..... 32 6.3.5 master / slave mode (bit 0) ............................................................................................. ...... 32 6.4 mclk frequency - address 05h .............................................................................................. ...... 33 6.4.1 master clock dividers (bits 6:4) ........................................................................................ .... 33 6.5 pgaout control - address 06h .............................................................................................. ........ 33 6.5.1 pgaout source select (bit 6) ............... ............................................................................. ... 33 6.6 channel b pga control - address 07h ....................................................................................... ... 33
ds658f2 3 cs5345 6.6.1 channel b pga gain (bits 5:0) ........................................................................................... .. 33 6.7 channel a pga control - address 08h ....................................................................................... ... 34 6.7.1 channel a pga gain (bits 5:0) ........................................................................................... .. 34 6.8 adc input control - address 09h ........................................................................................... ........ 34 6.8.1 pga soft ramp or zero cross enable (bits 4:3) .................................................................. 34 6.8.2 analog input selection (bits 2:0) ....................................................................................... .... 35 6.9 active level control - address 0ch ........................................................................................ ........ 35 6.9.1 active high/low (bit 0) ................................................................................................. ......... 35 6.10 interrupt status - address 0dh ........................................................................................... .......... 35 6.10.1 clock error (bit 3) .................................................................................................... ............ 36 6.10.2 overflow (bit 1) ....................................................................................................... ............. 36 6.10.3 underflow (bit 0) ...................................................................................................... ............ 36 6.11 interrupt mask - address 0eh ............................................................................................. .......... 36 6.12 interrupt mode msb - address 0fh .............. ........................................................................... ..... 36 6.13 interrupt mode lsb - addr ess 10h ......................................................................................... ...... 36 7. parameter definitions ...................................................................................................... .......... 37 8. filter plots ............................................................................................................ ...................... 38 9. package dimensions ......................................................................................................... ........... 40 10. thermal characteristics and specifications ............................................................. 40 11. ordering information ................................................................................................ ........ 41 12. revision history .......................................................................................................... ................ 41 list of figures figure 1.master mode serial audio port timing ................................................................................. ...... 18 figure 2.slave mode serial audio port timing .................................................................................. ....... 18 figure 3.format 0, left-justified up to 24-bit data ........................................................................... ........ 19 figure 4.format 1, i2s up to 24-bit data ...................................................................................... ............. 19 figure 5.control port timing - i2c format ....... .............................................................................. ............ 20 figure 6.control port timing - spi format ..................................................................................... ........... 21 figure 7.typical connection diagram .................... ....................................................................... ............ 22 figure 8.master mode clocking ................................................................................................. ............... 24 figure 9.analog input architecture ............................................................................................ ................ 25 figure 10.control port timing in spi mode ..................................................................................... ......... 26 figure 11.control port timing, i2c write ...................................................................................... ............. 27 figure 12.control port timing, i2c read ....................................................................................... ............ 27 figure 13.single- speed stopband rejection ..................................................................................... ....... 38 figure 14.single- speed stopband rejection ..................................................................................... ....... 38 figure 15.singl e-speed transition band (detail) ............................................................................... ....... 38 figure 16.single-speed passband ripple ........................................................................................ ........ 38 figure 17.double-speed st opband rejection ..................................................................................... ...... 38 figure 18.double-speed st opband rejection ..................................................................................... ...... 38 figure 19.double-speed transition band (detail) ............................................................................... ..... 39 figure 20.double-speed passband ripple ............... ......................................................................... ....... 39 figure 21.quad-speed stopband rejection ....................................................................................... ...... 39 figure 22.quad-speed stopband rejection ....................................................................................... ...... 39 figure 23.quad-s peed transition band (det ail) ................................................................................. ...... 39 figure 24.quad-sp eed passband ripple .......................................................................................... ....... 39 list of tables table 1. speed modes .......................................................................................................... .................... 23 table 2. common clock frequencies ............................................................................................. .......... 23 table 3. slave mode serial bit clock ratios ................................................................................... .......... 24 table 4. device revision ...................................................................................................... .................... 31
4 ds658f2 cs5345 table 5. freeze-able bits ..................................................................................................... ..................... 31 table 6. functional mode sele ction ............................................................................................ .............. 32 table 7. digital interface formats ............................................................................................ ................. 32 table 8. mclk frequency ....................................................................................................... ................. 33 table 9. pgaout source select ion .............................................................................................. ............. 33 table 10. example gain and attenuation settings ............................................................................... .... 34 table 11. pga soft cross or zero cross mode select ion ........................................................................ 3 5 table 12. analog input multiplexe r selection .................................................................................. .......... 35
ds658f2 5 cs5345 1. pin descriptions pin name # pin description sda/cdout 1 serial control data ( input / output ) - sda is a data i/o in i2c ? mode. cdout is the output data line for the control port interface in spi tm mode. scl/cclk 2 serial control port clock ( input ) - serial clock for th e serial control port. ad0/cs 3 address bit 0 (i2c) / control port chip select (spi) (input) - ad0 is a chip address pin in i2c mode; cs is the chip-select signal for spi format. ad1/cdin 4 address bit 1 (i2c) / serial control data input (spi) (input) - ad1 is a chip address pin in i2c mode; cdin is the input data line for the c ontrol port interface in spi mode. vlc 5 control port power ( input ) - determines the required signal level fo r the control port interface. refer to the recommended operating conditions for appropriate voltages. reset 6 reset ( input ) - the device enters a low-power mode when this pin is driven low. ain3a ain3b 7 8 stereo analog input 3 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. ain2a ain2b 9 10 stereo analog input 2 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vls sda/cdout agnd ovfl scl/cclk ad0/cs ad1/cdin vlc reset ain3a ain3b ain2a ain2b ain1a ain1b va afiltb vq tsto filt+ tsto ain4a/micin1 ain4b/micin2 ain5a ain5b afilta tsto nc nc agnd agnd va pgaoutb pgaouta ain6b ain6a micbias int vd dgnd mclk lrck sclk sdout nc nc nc tsti cs5345
6 ds658f2 cs5345 ain1a ain1b 11 12 stereo analog input 1 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. agnd 13 analog ground ( input ) - ground reference for the internal analog section. va 14 analog power (input) - positive power for the internal analog section. afilta 15 antialias filter connection ( output ) - antialias filter connection for the channel a adc input. afiltb 16 antialias filter connection ( output ) - antialias filter connection for the channel b adc input. vq 17 quiescent voltage ( output ) - filter connection for the internal quiescent reference voltage. tsto 18 test pin ( output ) - this pin must be left unconnected. filt+ 19 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. tsto 20 test pin - this pin must be left unconnected. ain4a/micin1 ain4b/micin2 21 22 stereo analog input 4 / microphone input 1 & 2 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. ain5a ain5b 23 24 stereo analog input 5 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. micbias 25 microphone bias supply ( output ) - low-noise bias supply for external microphone. electrical charac- teristics are specified in the dc electrical characteristics specification table. ain6a ain6b 26 27 stereo analog input 6 ( input ) - the full-scale level is specified in the adc analog characteristics specification table. pgaouta pgaoutb 28 29 pga analog audio output ( output ) - either an analog output from the pga block or high impedance. see ?pgaout source select (bit 6)? on page 33 . va 30 analog power (input) - positive power for the internal analog section. agnd 31 32 analog ground ( input ) - ground reference for the internal analog section. nc 33 34 no connect - these pins are not connected internally a nd should be tied to ground to minimize any potential coupling effects. tsto 35 test pin ( output ) - this pin must be left unconnected. vls 36 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operating conditions for appropriate voltages. tsti 37 test pin ( input ) - this pin must be connected to ground. nc 38, 39, 40 no connect - these pins are not connected internally a nd should be tied to ground to minimize any potential coupling effects. sdout 41 serial audio data output ( output ) - output for two?s complement serial audio data. sclk 42 serial clock (input/output ) - serial clock for the serial audio interface. lrck 43 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 44 master clock ( input ) - clock source for the adc? s delta-sigma modulators. dgnd 45 digital ground ( input ) - ground reference for the internal digital section. vd 46 digital power ( input ) - positive power for the internal digital section. int 47 interrupt ( output ) - indicates an interrupt condition has occurred. ovfl 48 overflow ( output ) - indicates an adc overflow condition is present.
ds658f2 7 cs5345 2. characteristics and specifications specified operating conditions agnd = dgnd = 0 v; all voltages with respect to ground. notes: 1. maximum of va+0.25 v or 5.25 v, whichever is less. absolute maximum ratings agnd = dgnd = 0 v all voltages with respect to ground. (note 2) 2. operation beyond these limits may result in permanent damage to the device. normal operation is not guar anteed at these extremes. 3. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. parameters symbol min nom max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc 3.13 3.13 1.71 1.71 5.0 3.3 3.3 3.3 5.25 (note 1) 5.25 5.25 v v v v ambient operating temperatur e (power applied) commercial automotive t a t a -10 -40 - - +70 +105 c c parameter symbol min max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc -0.3 -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 +6.0 v v v v input current (note 3) i in - 10 ma analog input voltage v ina agnd-0.3 va+0.3 v digital input voltage logic - serial port logic - control port v ind-s v ind-c -0.3 -0.3 vls+0.3 vlc+0.3 v v ambient operating temper ature (power applied) t a -50 +125 c storage temperature t stg -65 +150 c
8 ds658f2 cs5345 adc analog characteristics test conditions (unless otherwise s pecified): agnd = dgnd = 0 v; va = 3.13 v to 5.25 v; vd = 3.13 v to 5.25 v or va + 0.25 v, whichever is less ; vls = vlc = 1.71 v to 5.25 v; t a = -10 to +70 c for commercial or -40 to +85 c for automotive; input test signal: 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz; fs = 48/96/192 khz.; all connections as shown in figure 7 on page 22 . line-level inputs parameter symbol commercial grade automotive grade unit min typ max min typ max dynamic performance for va = 4.75 v to 5.25 v dynamic range pga setting: -12 db to +6 db a-weighted unweighted (note 6) 40 khz bandwidth unweighted pga setting: +12 db gain a-weighted unweighted (note 6) 40 khz bandwidth unweighted 98 95 - 92 89 - 104 101 98 98 95 92 - - - - - - 96 93 - 90 87 - 104 101 98 98 95 92 - - - - - - db db db db db db total harmonic distortion + noise (note 5) pga setting: -12 db to +6 db -1 db -20 db -60 db (note 6) 40 khz bandwidth -1 db pga setting: +12 db gain -1 db -20 db -60 db (note 6) 40 khz bandwidth -1 db thd+n - - - - - - - - -95 -81 -41 -92 -92 -75 -35 -89 -89 - - - -86 - - - - - - - - - - - -95 -81 -41 -92 -92 -75 -35 -89 -87 - - - -84 - - - db db db db db db db db dynamic performance for va = 3.13 v to 3.46 v dynamic range pga setting: -12 db to +6 db a-weighted unweighted (note 6) 40 khz bandwidth unweighted pga setting: +12 db gain a-weighted unweighted (note 6) 40 khz bandwidth unweighted 93 90 - 89 86 - 101 98 95 95 92 89 - - - - - - 91 88 - 87 84 - 101 98 95 95 92 89 - - - - - - db db db db db db total harmonic distortion + noise (note 5) pga setting: -12 db to +6 db -1 db -20 db -60 db (note 6) 40 khz bandwidth -1 db pga setting: +12 db gain -1 db -20 db -60 db (note 6) 40 khz bandwidth -1 db thd+n - - - - - - - - -92 -78 -38 -84 -89 -72 -32 -81 -86 - - - -83 - - - - - - - - - - - -92 -78 -38 -84 -89 -72 -32 -81 -84 - - - -81 - - - db db db db db db db db
ds658f2 9 cs5345 4. valid for the selected input pair. line-level inputs parameter symbol commercial grade a utomotive grade unit min typ max min typ max interchannel isolation - 90 - - 90 - db dc accuracy gain error - - 10 -- 10 % gain drift - 100 - - 100 - ppm/c line-level input characteristics full-scale input voltage 0.51*va 0.57*va 0.63*va 0.51*va 0.57*va 0.63*va v pp input impedance (note 4) 6.12 6.8 7.48 5.44 6.8 8.16 k maximum interchannel input impedance mismatch -5- -5-% line-level and microphone-level inputs parameter symbol commercial grade a utomotive grade unit min typ max min typ max dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db programmable gain characteristics gain step size - 0.5 - - 0.5 - db absolute gain step error - - 0.4 - - 0.4 db
10 ds658f2 cs5345 adc analog characteristics (continued) 5. referred to the typical line- level full-scale input voltage 6. valid for double- and quad-speed modes only. 7. valid when the microphone-level inputs are selected. microphone-level inputs parameter symbol commercial grade automotive grade unit min typ max min typ max dynamic performance for va = 4.75 v to 5.25 v dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - 75 72 63 60 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 5) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -80 -60 -20 -68 -74 - - - - - - - -80 -60 -20 -68 -72 - - - db db db db dynamic performance for va = 3.13 v to 3.46 v dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - 75 72 63 60 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 5) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -80 -60 -20 -68 -74 - - - - - - - -80 -60 -20 -68 -72 - - - db db db db interchannel isolation - 80 - - 80 - db dc accuracy gain error - 5 -- 5 -% gain drift - 300 - - 300 - ppm/c microphone-level input characteristics full-scale input voltage 0.013*va 0.017 *va 0.021*va 0.013*va 0.017*va 0.021*va v pp input impedance (note 7) -60- -60-k
ds658f2 11 cs5345 adc digital filter characteristics 8. filter response is guaranteed by design. 9. response shown is for fs = 48 khz. 10. response is clock-dependent and will scale wi th fs. note that the response plots ( figures 13 to 24 ) are normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. parameter (notes 8 , 10 ) symbol min typ max unit single-speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.035 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay (fs = output sample rate) t gd -12/fs - s double-speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.025 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd -9/fs - s quad-speed mode passband (-0.1 db) 0 - 0.2604 fs passband ripple - - 0.025 db stopband 0.5000 - - fs stopband attenuation 60 - - db total group delay (fs = output sample rate) t gd -5/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db (note 9) -1 20 - - hz hz phase deviation @ 20 hz (note 9) -10 -deg passband ripple -- 0db filter settling time 10 5 /fs s
12 ds658f2 cs5345 pgaout analog characteristics test conditions (unless otherwise sp ecified): agnd = dgnd = 0 v; va = 3.13 v to 5.25 v; vd = 3.13 v to 5.25 v or va + 0.25 v, whichever is less; vls = vlc = 1.71 v to 5.25 v; t a = -10 to +70 c for commercial or -40 to +85 c for automotive; input test signal: 1 khz si ne wave; measurement bandwidth: 10 hz to 20 khz; fs = 48/96/192 khz; synchronous mode ; all connections as shown in figure 7 on page 22 . 11. referred to the typical line-level full-scale input voltage. va = 4.75 v to 5.25 v parameter symbol commercial grade automotive grade unit min typ max min typ max dynamic performance with pga line-level input selected dynamic range pga setting: -12 db to +6 db a-weighted unweighted pga setting: +12 db gain a-weighted unweighted 98 95 92 89 104 101 98 95 - - - - 96 93 90 87 104 101 98 95 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to +6 db -1 db -20 db -60 db pga setting: +12 db gain -1 db -20 db -60 db thd+n - - - - - - -80 -81 -41 -80 -75 -35 -74 - - -74 - - - - - - - - -80 -81 -41 -80 -75 -35 -72 - - -72 - - db db db db db db dynamic performance with pga mic-level input selected dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - 75 72 63 60 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -74 -60 -20 -68 -68 - - - - - - - -74 -60 -20 -68 -66 - - - db db db db
ds658f2 13 cs5345 pgaout analog characteristics (continued) va = 3.13 v to 3.46 v parameter symbol commercial grade automotive grade unit min typ max min typ max dynamic performance with pga line-level input selected dynamic range pga setting: -12 db to +6 db a-weighted unweighted pga setting: +12 db gain a-weighted unweighted 93 90 89 86 101 98 95 92 - - - - 91 88 87 84 101 98 95 92 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to +6 db -1 db -20 db -60 db pga setting: +12 db gain -1 db -20 db -60 db thd+n - - - - - - -80 -78 -38 -80 -72 -32 -74 - - -74 - - - - - - - - -80 -78 -38 -80 -72 -32 -72 - - -72 - - db db db db db db dynamic performance with pga mic level-input selected dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - 75 72 63 60 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -74 -60 -20 -68 -68 - - - - - - - -74 -60 -20 -68 -66 - - - db db db db
14 ds658f2 cs5345 pgaout analog characteristics (continued) 12. guaranteed by design. va = 3.13 v to 5.25 v parameter symbol commercial grade automotive grade unit min typ max min typ max dc accuracy with pga li ne level input selected interchannel gain mismatch - 0.1 - - 0.1 - db gain error - 5- - 5- % gain drift - 100 - - 100 - ppm/c dc accuracy with pga mic level input selected interchannel gain mismatch - 0.3 - - 0.3 - db gain error - 5- - 5- % gain drift - 300 - - 300 - ppm/c analog output frequency response 10 hz to 20 khz (note 12) -0.1db - +0.1db -0.1db - +0.1db db analog in to analog out phase shift - 180 - - 180 - deg dc current draw from a pgaout pin i out --1--1 a ac-load resistance r l 100 - - 100 - - k load capacitance c l - - 20 - - 20 pf
ds658f2 15 cs5345 dc electrical characteristics agnd = dgnd = 0 v, all voltages with respect to ground. mclk=12.288 mhz; fs=48 khz; master mode. 13. power-down mode is defines as reset = low with all clock and data lines held static and no analog input. 14. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. 15. guaranteed by design. the dc current draw represen ts the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. parameter symbol min typ max unit power supply current va = 5 v (normal operation) va = 3.3 v vd, vls, vlc = 5 v vd, vls, vlc = 3.3 v i a i a i d i d - - - - 41 37 39 23 50 45 47 28 ma ma ma ma power supply current va = 5 v (power-down mode) (note 13) vls, vlc, vd=5 v i a i d - - 0.50 0.54 - - ma ma power consumption (normal operation) va, vd, vls, vlc = 5 v va, vd, vls, vlc = 3.3 v (power-down mode) va, vd, vls, vlc = 5 v - - - - - - 400 198 4.2 485 241 - mw mw mw power supply rejection ratio (1 khz) (note 14) psrr - 55 - db vq characteristics quiescent voltage vq - 0.5 x va - vdc dc current from vq (note 15) i q -- 1 a vq output impedance z q -23 -k filt+ nominal voltage filt+ - va - vdc microphone bias voltage micbias - 0.8 x va - vdc current from micbias i mb -- 2ma
16 ds658f2 cs5345 digital interface characteristics test conditions (unless otherwise specified): agnd = dgnd = 0 v; vls = vlc = 1.71 v to 5.25 v. 16. serial port signals include: mclk, sclk, lrck, sdout. control port signals include: scl/cclk, sda/cdout, ad0/cs , ad1/cdin, reset , int, ovfl. 17. guaranteed by design. parameters (note 16) symbol min typ max units high-level input voltage vl = 1.71 v serial port control port vl > 2.0 v serial port control port v ih v ih v ih v ih 0.8xvls 0.8xvlc 0.7xvls 0.7xvlc - - - - - - - - v v v v low-level input voltage serial port control port v il v il - - - - 0.2xvls 0.2xvlc v v high-level output voltage at i o = 2 ma serial port control port v oh v oh vls-1.0 vlc-1.0 - - - - v v low-level output voltage at i o = 2 ma serial port control port v ol v ol - - - - 0.4 0.4 v v input leakage current i in --10 a input capacitance (note 17) --1pf minimum ovfl active time - - s 10 6 lrck ---------------- -
ds658f2 17 cs5345 switching characteristics - serial audio port logic ?0? = dgnd = agnd = 0 v; logic ?1? = vl, c l = 20 pf. (note 18) 18. see figure 1 and figure 2 on page 18 . parameter symbol min typ max unit sample rate single-speed mode double-speed mode quad-speed mode fs fs fs 4 50 100 - - - 50 100 200 khz khz khz mclk specifications mclk frequency f mclk 1.024 - 51.200 mhz mclk input pulse width high/low t clkhl 8- -ns master mode lrck duty cycle - 50 - % sclk duty cycle - 50 - % sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 36 ns slave mode lrck duty cycle 405060% sclk period single-speed mode double-speed mode quad-speed mode t sclkw t sclkw t sclkw - - - - - - ns ns ns sclk pulse width high t sclkh 30 - - ns sclk pulse width low t sclkl 48 - - ns sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 36 ns 10 9 128 () fs -------------------- - 10 9 64 () fs ----------------- - 10 9 64 () fs ----------------- -
18 ds658f2 cs5345 slr t sdout sclk output lrck output sdo t slr t sdout sclk input lrck input sdo t sclkh t sclkl t sclkw t figure 1. master mode serial audio port timing figure 2. slave mode serial audio port timing
ds658f2 19 cs5345 figure 3. format 0, left-j ustified up to 24-bit data lrck sclk sdata +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 msb -1 -2 -3 -4 channel a - left channel b - right lsb lsb msb figure 4. format 1, i2s up to 24-bit data lrck sclk sdata +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 channel a - left channel b - right lsb msb lsb
20 ds658f2 cs5345 switching characteristics - control port - i2c format inputs: logic 0 = dgnd = agnd = 0 v, logic 1 = vlc, c l =30pf. 19. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. 20. guaranteed by design. parameter symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 19) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda (note 20) t rc , t rd -1s fall time scl and sda (note 20) t fc , t fd - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 5. control po rt timing - i2c format
ds658f2 21 cs5345 switching characteristics - control port - spi format inputs: logic 0 = dgnd = agnd = 0 v, logic 1 = vlc, c l =30pf. 21. data must be held for sufficient time to bridge the transition time of cclk. 22. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck -6.0mhz reset rising edge to cs falling t srs 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 21) t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 22) t r2 - 100 ns fall time of cclk and cdin (note 22) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh rst t srs figure 6. control po rt timing - spi format
22 ds658f2 cs5345 3. typical connection diagram vls 0.1 f +1.8v to +5v dgnd vlc 0.1 f +1.8v to +5v scl/cclk sda/cdout ad1/cdin reset 2 k see note 1 agnd ad0/cs note 1: resistors are required for i2c control port operation micro- controller 0.1 f va * capacitors must be c0g or equivalent digital audio capture lrck sdout mclk sclk pgaouta pgaoutb 2.2nf afilta afiltb ovfl 2.2nf 3.3 f 3.3 f 47 f 0.1 f vq filt+ 10 f agnd ** 2 k int 47 f ain1a left analog input 1 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain1b right analog input 1 ain2a left analog input 2 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain2b right analog input 2 ain3a left analog input 3 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain3b right analog input 3 ain4a/micin1 left analog input 4 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain4b/micin2 right analog input 4 ain5a left analog input 5 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain5b right analog input 5 ain6a left analog input 6 10 f 10 f 1800 pf 1800 pf 100 k 100 k 100 100 ain6b right analog input 6 micbias agnd 0.1 f * * * * * * * * * * * * nc nc nc nc nc tsti tsto tsto tsto 10 f +3.3v to +5v 0.1 f 10 f 0.1 f va vd +3.3v to +5v r l see note 2 note 2 the value of r l is dictated by the microphone carteridge. cs5345 figure 7. typical connection diagram
ds658f2 23 cs5345 4. applications 4.1 recommended power-up sequence 1. hold reset low until the power supply,mclk, and lrck are stable. in this state, the control port is reset to its default settings. 2. bring reset high. the device will remain in a low power st ate with the pdn bit set by default. the con- trol port will be accessible. 3. the desired register settings can be loaded while the pdn bit remains set. 4. clear the pdn bit to initiate the power-up sequence. 4.2 system clocking the cs5345 will operate at sa mpling frequencies from 4 k hz to 200 khz. this range is divided into three speed modes as shown in table 1 . 4.2.1 master clock mclk/lrck must maintain an integer ratio as shown in table 2 . the lrck frequency is equal to fs, the frequency at which audio samples for each channel are clocked out of the device. the fm bits (see ?func- tional mode (bits 7:6)? on page 32. ) and the mclk freq bits (see ?mclk frequency - address 05h? on page 33. ) configure the device to generate the proper clocks in master mode and receive the proper clocks in slave mode. table 2 illustrates several standa rd audio sample rates an d the required mclk and lrck frequencies. mode sampling frequency single-speed 4-50 khz double-speed 50-100 khz quad-speed 100-200 khz table 1. speed modes lrck (khz) mclk (mhz) 64x 96x 128x 192x 256x 384x 512x 768x 1024x 32 - --- 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1584 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 64 - - 8.1920 12.2880 16.3840 24.5760 32.7680 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 45.1584 - - 96 - - 12.2880 18.4320 24.5760 36.8640 49.1520 - - 128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - - 192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - - mode qsm dsm ssm table 2. common clock frequencies
24 ds658f2 cs5345 4.2.2 master mode as a clock master, lrck and sclk will operate as out puts. lrck and sclk are internally derived from mclk with lrck equal to fs and sclk equal to 64 x fs as shown in figure 8 . 4.2.3 slave mode in slave mode, sclk and lrck operate as inputs. the left/right clock signal must be equal to the sam- ple rate, fs, and must be synchronously derived from the supplied master clock, mclk. the serial bit clock, sclk, must be synchronously de rived from the master clock, mclk, and be equal to 128x, 64x, 48x or 32x fs, depending on the desired speed mode. refer to table 3 for required clock ra- tios. 4.3 high-pass filter a nd dc offset calibration when using operational amplifiers in the input circui try driving the cs5345, a small dc offset may be driven into the a/d converter. the cs5345 includes a high-pa ss filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding clicks when switching between devices in a mul- tichannel system. the high-pass filter continuously s ubtracts a measure of t he dc offset from the ou tput of the decimation filter. if the hpffreeze bit (see ?high-pass filter freeze (bit 1)? on page 32. ) is set during normal operation, the current value of the dc offset for the each channel is froz en and this dc offset will continue to be sub- tracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1. running the cs5345 with the high-pass filter enabled un til the filter settles. se e the digital filter char- acteristics section for filter settling time. 2. disabling the high-pass filter an d freezing the stored dc offset. a system calibration performed in th is way will eliminate offsets anywhere in the signal path between the calibration point and the cs5345. single-speed double-speed quad-speed sclk/lrck ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x table 3. slave mode serial bit clock ratios 256 128 64 4 2 1 00 01 10 00 01 10 lrck sclk 000 001 010 1 1.5 2 011 100 3 4 mclk fm bits mclk freq bits figure 8. master mode clocking
ds658f2 25 cs5345 4.4 analog input multipl exer, pga, and mic gain the cs5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (pga). the input multiplexer can select one of six poss ible stereo analog input sources and route it to the pga. analog inputs 4a and 4b are able to insert a +32 d b gain stage before the i nput multiplexer, allowing them to be used for microphone-level signals without the need for any external gain. the pga stage pro- vides 12 db of gain or attenuation in 0.5 db steps. figure 9 shows the architecture of the input multiplexer, pga, and microphone gain stages. the ? ?analog input selection (bits 2:0)? on page 35 ? outlines the bit settings necessary to control the input multiplexer and mic gain. ?channel b pga control - address 07h? on page 33 and ?channel a pga control - address 08h? on page 34 outline the register settings necessar y to control the pga. by default, line- level input 1 is selected, and the pga is set to 0 db. 4.5 input connections the analog modulator samples the i nput at 6.144 mhz (mclk=12.288 mhz). the digital filter will reject sig- nals within the stopband of the filter. however, th ere is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to the typical connection diagram for the recommended analog input circ uit that will attenuate no ise energy at 6.144 m hz. the use of capac- itors which have a large voltage coe fficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity. any unused analog input pairs should be left unconnected. 4.6 pga auxiliary analog output the cs5345 includes an auxiliary an alog output thro ugh the pgaout pins. thes e pins can be configured to output the analog input to the adc as selected by the input mux and gained or attenuated with the pga, or alternatively, they may be set to high-impedance. see the ? ?pgaout source select (bit 6)? on page 33 ? for information on co nfiguring the pga auxiliary analog output. the pga auxiliary analog output can so urce very little current. as curren t from the pgaout pins increases, distortion will increase. for this reason, a high-input impedance buffer must be used on the pgaout pins to achieve full performance. refer to the table in ?pgaout analog characteristics? on page 12 for accept- able loading conditions. pga mux +32 db ain1a ain2a ain3a ain4a/micin1 ain5a ain6a pga mux +32 db ain1b ain2b ain3b ain4b/micin2 ain5b ain6b analog input selection bits channel a pga gain bits channel b pga gain bits out to adc channel a out to adc channel b figure 9. analog input architecture
26 ds658f2 cs5345 4.7 control port desc ription and timing the control port is used to access the registers, allo wing the cs5345 to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with th e cs5345 acting as a slave device. spi mode is se- lected if there is a high-t o-low transition on the ad0/cs pin, after the reset pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vl c or dgnd, thereby permanently selecting the desired ad0 bit address state. 4.7.1 spi mode in spi mode, cs is the cs5345 chip-select signal; cclk is the co ntrol port bit clock (input into the cs5345 from the microcontroller); cdin is the input data line from the micr ocontroller; cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 10 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to writ e. the next eight bits form the memory address pointer (map), which is set to the address of the r egister that is to be updated. the next eight bi ts are the data that will be placed into the register desi gnated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k resistor, if desired. to read a register, the map has to be set to the co rrect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. to begin a read, bring cs low, send out the chip ad- dress and set the read/write bit (r/w ) high. the next falling edge of cc lk will clock out the msb of the addressed register (cdout will le ave the high-im pedance state). for both read and write cycles, th e memory address pointer will auto matically increment following each data byte in order to fac ilitate block reads an d writes of successive registers. 4.7.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocked into and ou t of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-sign ificant bits of the ch ip address and should map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 10. control port timing in spi mode
ds658f2 27 cs5345 be connected through a resistor to vlc or dgnd as desired. the state of the pins is sensed while the cs5345 is being reset. the signal timings for a read and write cycle are shown in figure 11 and figure 12 . a start condition is defined as a falling transition of sda while the clock is high. a stop condi tion is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs5345 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixe d at 10011. to communicate with a cs5345, the chip address field, which is the first byte sent to the cs5345, should match 10011 followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (m ap) which selects the register to be re ad or written. if the operation is a read, the contents of the register pointed to by the map will be outp ut. following each data byte, the mem- ory address pointer will auto matically increment to facilitate block reads and writes of successive regis- ters. each byte is separated by an acknowledge bit. the ack bit is output from the cs5345 after each input byte is read, and is input to the cs5345 fr om the microcontroller after each transmitted byte. since the read operation cannot set the map, an aborted write operation is used as a preamble. as shown in figure 12 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10011xx1(chip address & read operation). receive acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 6 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 11. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start 7 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 12. control port timing, i2c read
28 ds658f2 cs5345 receive byte, contents of selected register. send acknowledge bit. send stop condition. 4.8 interrupts and overflow the cs5345 has a comprehensive interrupt capability. the int output pin is intended to drive the interrupt input pin on the host microcontroller. the int pin may function as either an active high cmos driver or an active low open-drain driver (see ?active high/low (bit 0)? on page 35 ). when configured as active low open-drain, the int pin has no active pull-up transistor, allowing it to be used for wired-or hook-ups with multiple peripherals connected to t he microcontroller interrupt input pin. in this configuration, an external pull-up resistor must be placed on the int pin for proper operation. many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see ?interrupt status - address 0dh? on page 35 ). each source may be masked off through mask register bits. in addition, each source may be se t to rising edge, fa lling edge, or level-sensitive. co mbined with the option of level- sensitive or edge-sensitive modes with in the microcontroller, many different configurations are possible, de- pending on the needs of the equipment designer. the cs5345 also has a dedicated overflow output. th e ovfl pin functions as active low open drain and has no active pull-up transistor, thereby requiring an ex ternal pull-up resistor. the ovfl pin outputs an or of the adcoverflow and adcunderflow c onditions available in the interrupt status register; however, these conditions do not need to be unmasked for proper operation of the ovfl pin. 4.9 reset when reset is low, the cs5345 enters a low-power mode and all internal states are reset, including the control port and registers, the outputs are muted. when reset is high, the control port becomes operation- al, and the desired settings should be loaded into the control registers. writing a 0 to the pdn bit in the pow- er control register will then c ause the part to leave the low- power state and begin operation. the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of po wer or by setting the reset pin high. however, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the filt+ pin. during this voltage referenc e ramp delay, sdout will be automatically muted. it is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues. 4.10 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronou s sampling, the master clocks and left/righ t clocks must be the same for all of the cs5345s in the system. if only one master clock source is needed, one solution is to place one cs5345 in master mode, and slave all of the other cs5345s to th e one master. if multiple master clock sources are needed, a possible solution would be to supply all cl ocks from the same external source and time the cs5345 reset with the inactive edge of master clock. this will ensure that all conv erters begin sampling on the same clock edge. 4.11 grounding and power supply decoupling as with any high-resolution converter, the cs5345 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 7 shows the recommended power ar- rangements, with va connected to a clean supply. vd, which powers the digital filter, may be run from the
ds658f2 29 cs5345 system logic supply (vls or vlc) or may be powered from the analog supply (va) via a resistor. in this case, no additional devices should be powered from vd. power supply decoupling capacitors should be as near to the cs5345 as possible, with the low value ce ramic capacitor being the nearest. all signals, espe- cially clocks, should be kept away fr om the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, pa rticularly the 0.1 f, must be positioned to mini- mize the electrical path from filt+ and agnd. th e cs5345 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the cs5345 digital outputs only to cmos inputs.
30 ds658f2 cs5345 5. register qu ick reference this table shows the register names and their associated default values. addr function 7 6 5 4 3 2 1 0 01h chip id part3 part2 part1 part0 rev3 rev2 rev1 rev0 11100001 02h power control freeze reserved reserved reserved pdn_mic pdn_adc reserved pdn 00000001 03h reserved reserved reserved reserved reserved reserved reserved reserved reserved 00001000 04h adc control fm1 fm0 reserved dif reserved mute hpffreeze m/s 00000000 05h mclk frequency reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved 00000000 06h pgaout control reserved pgaout reserved reserved re served reserved reserved reserved 01000000 07h pga ch b gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 00000000 08h pga ch a gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 00000000 09h analog input control reserved reserved reserved pgasoft pgazero sel2 sel1 sel0 00011001 0ah - 0bh reserved reserved reserved reserved rese rved reserved reserved reserved reserved 00000000 0ch active level control reserved reserved reserved reserved re served reserved reserved active_h/l 11000000 0dh interrupt status reserved reserved reserved reserved clkerr reserved ovfl undrfl 00000000 0eh interrupt mask reserved reserved reserved reserved clkerrm reserved ovflm undrflm 00000000 0fh interrupt mode msb reserved reserved reserved reserv ed clkerr1 reserved ovfl1 undrfl1 00000000 10h interrupt mode lsb reserved reserved reserved reserv ed clkerr0 reserved ovfl0 undrfl0 00000000
ds658f2 31 cs5345 6. register description 6.1 chip id - register 01h function: this register is read-only. bits 7 through 4 are the pa rt number id, which is 1110b (0eh), and the remaining bits (3 through 0) indicate the device revision as shown in table 4 below. 6.2 power control - address 02h 6.2.1 freeze (bit 7) function: this function allows modifications to be made to cert ain control port bits without the changes taking effect until the freeze bit is disabled. to make multiple chang es to these bits take effe ct simultaneously, set the freeze bit, make all changes, then clear the freeze bit. the bits affected by the freeze function are listed in table 5 . 6.2.2 power-down mic (bit 3) function: the microphone preamplifier blo ck will enter a low-power state whenever this bit is set. 6.2.3 power-down adc (bit 2) function: the adc pair will remain in a reset state whenever this bit is set. 6.2.4 power-down device (bit 0) function: the device will enter a low-power stat e whenever this bit is set. the powe r-down bit is se t by default and must be cleared before normal operation can occur. the contents of the control registers are retained when the device is in power-down. 76543210 part3 part2 part1 part0 rev3 rev2 rev1 rev0 rev[2:0] revision 001 a 010 b, c0 011 c1 table 4. device revision 76543210 freeze reserved reserved reserved pdn_mic pdn_adc reserved pdn name register bit(s) mute 04h 2 gain[5:0] 07h 5:0 gain[5:0] 08h 5:0 table 5. freeze-able bits
32 ds658f2 cs5345 6.3 adc control - address 04h 6.3.1 functional mode (bits 7:6) function: selects the required range of sample rates. 6.3.2 digital interface format (bit 4) function: the required relationship between lrck, sclk and sd out is defined by the digital interface format bit. the options are detailed in table 7 and may be seen in figure 3 and figure 4 . 6.3.3 mute (bit 2) function: when this bit is set, the serial audio output of the both channels is muted. 6.3.4 high-pass filter freeze (bit 1) function: when this bit is set, the in ternal high-pass filter is disabled.the current dc offset valu e will be frozen and continue to be subtracted from the conversion result. see ?high-pass filter and dc offset calibration? on page 24. 6.3.5 master / slave mode (bit 0) function: this bit selects either master or slave operation for the serial audio port. setting this bit selects master mode, while clearing this bit selects slave mode. 76543210 fm1 fm0 reserved dif reserved mute hpffreeze m/s fm1 fm0 mode 0 0 single-speed mode: 4 to 50 khz sample rates 0 1 double-speed mode: 50 to 100 khz sample rates 1 0 quad-speed mode: 100 to 200 khz sample rates 11reserved table 6. functional mode selection dif description format figure 0 left-justified, up to 24-bit data (default) 0 3 1 i2s, up to 24-bit data 1 4 table 7. digital interface formats
ds658f2 33 cs5345 6.4 mclk frequency - address 05h 6.4.1 master clock dividers (bits 6:4) function: sets the frequency of the supplied mclk signal. see table 8 for the appropriate settings. 6.5 pgaout contro l - address 06h 6.5.1 pgaout source select (bit 6) function: this bit is used to configure the pgaout pins to be either high impedance or pga outputs. refer to table 9 . 6.6 channel b pga c ontrol - a ddress 07h 6.6.1 channel b pga gain (bits 5:0) function: see ?channel a pga gain (bits 5:0)? on page 34. 76543210 reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved mclk divider mclk freq 2 mclk freq1 mclk freq0 1 000 1.5 001 2 010 3 011 4 100 reserved 101 reserved 11x table 8. mclk frequency 76543210 reserved pgaout reserved reserved re served reserved reserved reserved pgaout pgaouta & pgaoutb 0 high impedance 1 pga output table 9. pgaout source selection 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0
34 ds658f2 cs5345 6.7 channel a pga control - address 08h 6.7.1 channel a pga gain (bits 5:0) function: sets the gain or attenuation for the adc input pga stage. the gain may be adjusted from -12 db to +12 db in 0.5 db steps. the gain bits are in two?s co mplement with the gain0 bit set for a 0.5 db step. register settings outside of the 12 db rang e are reserved and must not be used. see table 10 for ex- ample settings. 6.8 adc input control - address 09h 6.8.1 pga soft ramp or zero cross enable (bits 4:3) function: soft ramp enable soft ramp allows level changes, bo th muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the ne w level at a rate of 1 db per 8 left/right clock periods. see table 11 . zero cross enable zero cross enable dictates that si gnal-level changes, either by atte nuation changes or muting, will occur on a signal zero crossing to minimize audible arti facts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 11 . soft ramp and zero cross enable soft ramp and zero cross enable di ctate that signal-level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a signal zero cr ossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sam- ple rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. see table 11 . 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 gain[5:0] setting 101000 -12 db 000000 0 db 011000 +12 db table 10. example gain and attenuation settings 76543210 reserved reserved reserved pgasoft pgazero sel2 sel1 sel0
ds658f2 35 cs5345 6.8.2 analog input selection (bits 2:0) function: these bits are used to select the input source for the pga and adc. please see table 12 . 6.9 active level control - address 0ch 6.9.1 active high/low (bit 0) function: when this bit is set, the int pin functi ons as an active high cmos driver. when this bit is cleared, the int pi n functions as an active low open drain driver and will require an exter- nal pull-up resistor for proper operation. 6.10 interrupt status - address 0dh for all bits in this register, a ?1? means the associat ed interrupt condition has occurred at least once since the register was last read. a ?0? means the associat ed interrupt condition has not occurred since the last reading of the register. status bits that are masked off in the associ ated mask register will always be ?0? in this register. this register defaults to 00h. pgasoft pgazerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled (default) table 11. pga soft cross or zero cross mode selection sel2 sel1 sel0 pga/adc input 0 0 0 microphone-level inputs (+32 db gain enabled) 0 0 1 line-level input pair 1 0 1 0 line-level input pair 2 0 1 1 line-level input pair 3 1 0 0 line-level input pair 4 1 0 1 line-level input pair 5 1 1 0 line-level input pair 6 1 1 1 reserved table 12. analog input multiplexer selection 76543210 reserved reserved reserved reserved reserved reserved reserved active_h/l 76543210 reserved reserved reserved reserved clkerr reserved ovfl undrfl
36 ds658f2 cs5345 6.10.1 clock error (bit 3) function: indicates the occurrence of a clock error condition. 6.10.2 overflow (bit 1) function: indicates the occurrence of an adc overflow condition. 6.10.3 underflow (bit 0) function: indicates the occurrence of an adc underflow condition. 6.11 interrupt mask - address 0eh function: the bits of this register se rve as a mask for the status sources found in the register ?interrupt status - ad- dress 0dh? on page 35 . if a mask bit is set to 1, the error is unmasked , meaning that its occurrence will affect the int pin and the status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the int pin or the status register. the bit positions align with the corresponding bits in the sta- tus register. 6.12 interrupt mode msb - address 0fh 6.13 interrupt mode lsb - address 10h function: the two interrupt mode registers form a 2-bit code fo r each interrupt status register function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising-edge active mode, the int pin becomes acti ve on the arrival of the interrupt cond ition. in the falling- edge active mode, the int pin becomes active on the removal of the inte rrupt condition. in level-ac tive mode, the int pin re- mains active during the interrupt condition. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 76543210 reserved reserved reserved reserved clkerrm reserved ovflm undrflm 76543210 reserved reserved reserved reserved clkerr1 reserved ovfl1 undrfl1 reserved reserved reserved reserved clkerr0 reserved ovfl0 undrfl0
ds658f2 37 cs5345 7. parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the spec ified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with no signal to the input under test and a full-sc ale signal applied to the ot her channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain drift the change in gain value with temperature. units in ppm/c.
38 ds658f2 cs5345 8. filter plots figure 13. single-speed stopband rejection figure 14. single-speed stopband rejection figure 15. single-speed transition band (det ail) figure 16. single-speed passband ripple figure 17. double-speed stopband rejection figure 18. double-speed stopband rejection -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.0 5 0.1 0 .15 0 .2 0.2 5 0 .3 0.3 5 0.4 0 .45 0 .5 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db)
ds658f2 39 cs5345 figure 19. double-speed transition band (det ail) figure 20. double-speed passband ripple figure 21. quad-speed stopband rejection figure 22. quad-speed stopband rejection figure 23. quad-speed transition band (d etail) figure 24. quad-speed passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (normalized to fs) amplitude (db)
40 ds658f2 cs5345 9. package dimensions 10.thermal characteristics and specifications 1. ja is specified according to jedec sp ecifications for multi-layer pcbs. inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm *controlling di mension is mm. *jedec designation: ms022 parameters symbol min typ max units package thermal resistance (note 1) 48-lqfp ja jc - - 48 15 - - c/watt c/watt allowable junction temperature --125 c 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds658f2 41 cs5345 11.ordering information 12.revision history product description package pb-free grade temp range container order # cs5345 24-bit, 192 khz stereo audio adc 48-lqfp yes commercial -10 to +70 c tray CS5345-CQZ tape & reel CS5345-CQZr cs5345 24-bit, 192 khz stereo audio adc 48-lqfp yes automotive -40 to +105 c tray cs5345-dqz tape & reel cs5345-dqzr cdb5345 cs5345 evaluation board no - - - cdb5345 release changes f1 ? removed the map auto-increment functional description from the control port description and timing section beginning on page 26 . ? added device revision information to the chip id - register 01h description on page 31 . f2 ? added automotive grade ? changed mclk to input only in the pin descriptions table on page 5 . ? updated the adc analog characteristics table on page 8 . ? updated the pgaout analog characteristics table on page 12 . ? updated the dc electrical characteristics table on page 15 . ? updated the digital interface characteristics table on page 16 . ? updated the switching characteristics - serial audio port table on page 17 . ? updated the switching characteristics - control port - spi format table on page 21 . ? updated the typical connection diagram on page 22 . ? switched channel b pga control - address 07h on page 33 and channel a pga control - address 08h on page 34 . contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. i nclusion of cirrus products in su ch applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or cus tomer?s customer uses or permits the use of ci rrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its o fficers, directors, employee s, distributors and other agents from any and all liability, including attorneys? fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

▲Up To Search▲

Price & Availability of CS5345-CQZ

	To Download CS5345-CQZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .